In the field of electronics various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed.
Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package. Before a design engineer programs the PLD though, a PLD is tested by its manufacturer using tests such as logic array tests, memory tests, I/O tests, fault coverage tests, etc.
But, as integrated circuits become more and more complex, testing costs become higher and higher. The time and effort involved in testing these PLDs before they are sold to a customer is increasing. Likewise, the complexity of newer PLDs means that it takes more time and effort for a design engineer to debug a PLD. In the course of generating a design for a PLD, programming the PLD and checking its functionality on the circuit board or in the system for which it is intended, it is important to be able to debug the PLD because a design is not always perfect the first time.
One approach to debugging a hardware device within a working system is to use a separate piece of hardware equipment called a logic analyzer to analyze signals present on the pins of a hardware device. Embedding a logic analyzer within the hardware device is another technique used. For example, U.S. Pat. No. 6,182,247 entitled “Embedded Logic Analyzer For A Programmable Logic Device” discloses such a technique, and U.S. Pat. Nos. 6,286,114 and 6,247,147 disclose enhancements. In addition, viewing internal nodes in a device may be performed as disclosed in U.S. patent application Ser. No. 09/802,480. Embedding a logic analyzer into a design is also a technique used in the product “ChipScope ILA” available from Xilinx Inc., of San Jose, Calif. The product “ChipScope Pro” also available from Xilinx uses logic cores built directly into a PLD to allow a user to access internal signals and nodes for debugging.
Although the above techniques are useful, the increasing complexity of integrated circuits slows the speed at which testing and debugging of integrated circuits can occur. For example, during hardware emulation on chip, testing or debugging may be slow. Testing or debugging is slow because of the speed of the external computer being used, the serial port on the device through which data and patterns must be passed, the necessary data gathering on the chip itself, and the presence of any probes used in the device. All these factors contribute to an emulation that becomes slower as chip complexity increases. One technique used for emulation available from Cadence and Synopsys involves a huge array of FPGAs in a hardware box. Numerous microprocessors load the FPGAs in order to simulate a hardware device for emulation. These emulation machines though, are extremely expensive.
A software simulation of an integrated circuit is also effected by increasing device complexity. During simulation, a software representation of the chip on a host computer is stimulated to produce outputs. Because the simulation model might be inaccurate, extensive testing is needed. Further, the host computer itself may be slow. Thus, the more complex the device, the slower the simulation goes.
What is desired is a technique for speeding up the process of testing and debugging integrated circuits such as programmable logic devices.